As it is well known, in power electronic devices, in particular in power devices of the MOS type, it is important to have the possibility of operating at higher and higher frequencies while maintaining a high component reliability.
Nowadays the uses of MOS devices in fact often require the possibility of operating, both at low supply voltage (20-100V) and at high supply voltage (200-1000V), but, however, at higher and higher frequencies approaching one megahertz (MHz).
Power devices are thus subjected to very high voltage and current gradients during the transients and/or during the switchings, which may make the stresses to the device weakening the same burdensome and reduce its lifetime drastically.
As it is well known, some power MOS devices are realized by thousands or millions of elementary MOS transistors placed in parallel and individually contributing to the overall current capacity of the device.
Typically, elementary MOS transistors, as highlighted in FIG. 1, are realized on semiconductor or with polygonal cells or strips and they comprise a body region, which, in the case shown, is of the p type, formed on a suitable substrate, of the n type, and with a source region realized on top.
The body region, together with the source region, form a channel region covered by an insulating layer, for example a silicon oxide, and by a conductive layer, for example suitably doped polysilicon.
These two insulating and conductive layers represent, for each elementary MOS transistor, the gate dielectric and for the power MOS device they form a biasing mesh also called the gate mesh.
The gate mesh is connected to a terminal called gate pad and it allows the distributing of the signals inside the MOS device as well as the turning on and/or off all the elementary MOS transistors composing the power MOS device.
The gate mesh, due to the high polysilicon resistivity (>10 Ohm/[square]), exhibits resistive contributions along the path which depend on the relative position with respect to the gate pad, as highlighted in the circuit of FIG. 2. This implies that gate resistance value of each elementary transistor also depends on the distance from the gate pad.
Thus, at each switching of the MOS device, each elementary MOS transistor responds with a time constant which will be distinct, being, as known, a function of the input capacitance and of the gate resistance.
The gate resistance is thus an important value because, together with the input capacity of the MOS device, forms an RC circuit whose time constant is one of the most important parameters influencing the switch speed of power electronic MOS devices. These latter devices, having to operate at higher and higher frequencies, require a more and more reduced time constant. Consequently, there is then an attempt to reduce the gate resistance and to make it homogeneous for the entire MOS device so as to ensure a good reliability even at high frequency.
To try and solve such problem, a known technique is that of carrying out a suitable metallization of the gate, a process including creating connection buses, also called gate fingers, realized in metallic material, so as to connect the gate pad to various points of the gate mesh by “short-circuiting” them, as shown in FIG. 3 and in the corresponding circuit of FIG. 4.
A related technique is that of increasing the number of gate fingers so as to intersect the gate mesh at a greater number of points.
Although advantageous in several aspects, such a solution exhibits different drawbacks, the main one being that the presence of the gate fingers realized in metallic material reduces the active area of the power MOS device, since below the gate fingers it is often not possible to integrate the elementary MOS transistors.
Moreover, a further drawback linked to the presence of the gate fingers is due to the fact that they may limit the number and the position of the wires connecting to the source pad, thus negatively affecting the output resistance of the power MOS device.
A further known solution to reduce the gate resistance provides the decrease of the gate mesh resistance by integrating there inside a highly conductive layer. Referring to FIG. 5, such a process makes use of metallic silicides, such as for example cobalt silicide (CoSi2), platinum silicide (PtSi), titanium silicide (TiSi2) or tungsten silicide (WSi2), which exhibit a layer resistivity of about one order of magnitude lower with respect to that of the unsilicided polysilicon.
For power electronic MOS devices used in faster and faster applications with low gate resistance, problems, however, emerge linked to the great voltage and current gradients during the transients.
FIG. 5 highlights a pattern in parallel of a pair of elementary MOS transistors which exhibit different gate resistances according to the position wherein they are with respect to the gate pad and to the gate fingers.
The diagram in FIG. 6 shows how between elementary MOS transistors where there exists an unbalance in the resistance value, during a switching step of the MOS device, different wave forms are produced which distribute the current at stake in a non uniform way. In particular it can be verified how the current intensity I2 crossing the slowest component, undergoes sudden increases negatively affecting the uniformity of the time constant of the electronic MOS device.
Such behavior in the power MOS device is exponentially increased relative to an increase in the plurality of elementary MOS transistors. This, however, may jeopardize both the correct functionality and the operating lifetime of the MOS device itself.
For the manufacturing process used in the realization of a power electronic MOS device, it is inevitable that there are unbalances in the current flow. In fact it is good to remember that the distance between one gate finger and the other is around 200-2000 μm and in such space many elementary MOS transistors are disposed whose gate biasing occurs by means of the gate mesh. In such case the elementary MOS transistors closer to the gate fingers often will be the fastest while the others will often be slower and slower, as highlighted in FIG. 7.
Further unbalances are due to the fact that because for problems due to the assembling step it is often difficult to realize continuous and equidistant gate fingers. Thus, the power MOS device obtained will exhibit areas with different distances between the gate fingers, as shown in the example of FIG. 8, and this implies the presence of a gate resistance influenced by the area with a shorter distance between the gate fingers, since in the calculation of the total resistance of these parallel resistances the areas with higher resistance will have less weight.
Moreover, it is good to reveal that although the resistivity of the material used for realizing the gate fingers is low, it is possible that the lengths of the fingers is such as to introduce resistive contributions that are significant as compared with the total gate resistance of the power electronic MOS device especially if, for lowering the metallization mesh resistance, metallic silicides are used.
As highlighted in the example of FIG. 9 and in the associated circuit of FIG. 10, the areas in correspondence with the points A and B, although being near the gate finger, exhibit a different resistance in series due to the contribution of the gate finger section AB, which could have an even higher resistance than one Ohm, with a consequent unbalance between the different areas of the power MOS device.
Considering for example a width of the metallic tracks of the gate finger equal to 10-50 μm, a thickness of the metallic layer between 2-10 μm and fixing at 5 mm the width of an aluminum track, the values of the minimum resistance of the gate finger will be approximately equal to 0.3 Ohm and the highest equal to approximately 7 Ohm.
It is good to remember that, in a fast power MOS device there is often the need of having a total gate resistance less than or equal to 1 Ohm, and then the importance is understood of reducing or voiding the resistive contributions of the gate fingers.
All these causes lead to having power electronic MOS devices weakened by the presence of areas having different gate resistances with consequent negative effects on the switches and during the extreme dynamic stresses during which there are high values of dV/dt and/or dl/dt.
The unbalance can also cause current localizations that can cause the incorrect operation and/or the destruction of the power MOS device.